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HT46R64/HT46C64 8-Bit A/D with LCD Type MCU
Features
* Operating voltage: * Watchdog Timer * Buzzer output * On-chip crystal, RC and 32768Hz crystal oscillator * HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 24 bidirectional I/O lines * Two external interrupt input * One 8-bit and one 16-bit programmable timer/event
consumption
* 8-level subroutine nesting * 8 channels 10-bit resolution A/D converter * 4-channel 8-bit PWM output shared with 4 I/O lines * Bit manipulation instruction * 16-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock * 63 powerful instructions * All instructions in 1 or 2 machine cycles * 56-pin SSOP, 100-pin QFP package
counter with PFD (programmable frequency divider) function
* LCD driver with 333 or 324 segments
(logical output option for SEG0~SEG15)
* 4K15 program memory * 1928 data memory RAM * Supports PFD for sound generation * Real Time Clock (RTC) * 8-bit prescaler for RTC
General Description
The HT46R64/HT46C64 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D product applications that interface directly to analog signals and which require LCD Interface. The mask version HT46C64 is fully pin and functionally compatible with the OTP version HT46R64 device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, HALT and wake-up functions, in addition to a flexible and configurable LCD interface enhance the versatility of these devices to control a wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc., for both industrial and home appliance application areas. HT46C64 under development, available in 1Q, 2004.
Rev. 1.00
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HT46R64/HT46C64
Block Diagram
In te rru p t C ir c u it P ro g ra m EPROM P ro g ra m C o u n te r STACK IN T C TM R0C TM R0 P.D0 TM R1C TM R1 P.D1 M U X M U X P r e s c a le r P D 6 /T M R 0 P D 7 /T M R 1 fS
YS
fS
YS
/4
32768Hz fS M U X /4 OSC3 OSC4
In s tr u c tio n R e g is te r
MP
M U
RTC X DATA M e m o ry W DT T im e B a s e
YS
RTC
OSC
W DT OSC
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
PW PDC STATUS PD
M PORT D
S h ifte r 8 -C h a n n e l A /D C o n v e rte r BP PBC PB LCD M e m o ry L C D D R IV E R PORT B
PD PD PD PD PD
0/ 4/ 5/ 6/ 7/
PW IN IN TM TM
M 0 ~ P D 3 /P W T0 T1 R0 R1
M3
OSC2 OSC4
OS RE VD VS OS S
D
S
C1
ACC
P B 0 /A N 0 ~ P B 7 /A N 7 PA0 PA1 PA2 PA3 PA4 /B Z /B Z /P . D ~PA7
C3
PAC PA H ALT
PORT A
E N /D IS
C O M 0~ COM2
C O M 3/ SEG 32
SEG 0~ SEG 31
L V D /L V R
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HT46R64/HT46C64
Pin Assignment
SEG N N N N N N N N OSC OSC VD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P . PA
P A 0 /B Z 1 2 3 4 5 6 7 8 9 P A 1 /B Z PA2 P A 3 /P . D PA4 PA5 PA6 PA7 P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 P B 4 /A N 4 P B 5 /A N 5 VSS P D 0 /P W M 0 P D 1 /P W M 1 P D 2 /P W M 2 P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 VLCD VMAX V1 V2 C1 C2 COM0
56 55 54 53 52 51 50 49 48 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
RES OSC1 OSC2 VDD OSC3 OSC4 SEG8 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20
P P P P PA N N N N N PA PA P B 0 /A N P B 1 /A N P B 2 /A N P B 3 /A N P B 4 /A N P B 5 /A N P B 6 /A N P B 7 /A N VS D 0 /P W M D 1 /P W M D 2 /P W M D 3 /P W M P D 4 /IN T P D 5 /IN T D 6 /T M R D 7 /T M R N N N N N C C C C C 6 7 0 1 2 3 4 5 6 7 S 0 1 2 3 0 1 0 1 C C C C C 9 8 7 6 5 4 3 P P 5 2 1
D D C C C C C C C C S Z Z 1 3 4 2
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
4 2 0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
H T 4 6 R 6 4 /H T 4 6 C 6 4 1 0 0 Q . P -A
SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 C O M 3 /S E G 3 2 COM2 COM1
SE SE SE NC NC NC SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE NC NC NC NC NC NC
G1 G2 G3
G4 G5 G6 G7 G8 G9 G1 G1 G1 G1 G1 G1 G1 G1 G1 G1 G2 G2 1
0 1 2 3 4 5 6 7 8 9 0
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VMA VLC D 22 23 24 25 26 27 28 29 30 31 3 /S E G 3 2 X 0 1 2
H T 4 6 R 6 4 /H T 4 6 C 6 4 5 6 S S O P -A
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HT46R64/HT46C64
Pin Description
Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PD0/PWM0 PD1/PWM1 PD2/PWM2 PD3/PWM3 PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1 VSS VLCD VMAX V1, V2, C1, C2 COM0~COM2 COM3/SEG32 SEG0~SEG31 I/O Options Wake-up Pull-high Buzzer PFD Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by option. Software instructions determine the CMOS output or Schmitt Trigger input with or without pull-high resistor (determined by pull-high options: bit option). The BZ, BZ and PFD are pin-shared with PA0, PA1 and PA3, respectively.
I/O
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically.
I/O
Pull-high PWM
Bidirectional 4-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The PWM0/PWM1/PWM2/PWM3 output function are pin-shared with PD0/PD1/PD2/PD3 (dependent on PWM options). Bidirectional 4-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The INT0, INT1, TMR0 and TMR1 are pin-shared with PD4/PD5/PD6/PD7. Negative power supply, ground LCD power supply IC maximum voltage connect to VDD, VLCD or V1 Voltage pump SEG32 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are outputs for LCD panel plate. LCD driver outputs for LCD panel segments. SEG0~SEG23 can be optioned as logical outputs. OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be floating. Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor Positive power supply Schmitt trigger reset input, active low
I/O
Pull-high
3/4 I I I O O
3/4 3/4 3/4 3/4 1/3 or 1/4 Duty Logical Output
OSC1 OSC2
O I
Crystal or RC
OSC3 OSC4 VDD RES
O I 3/4 I
RTC or System Clock 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT46R64/HT46C64
D.C. Characteristics
Test Conditions Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current Operating Current (fSYS=32768Hz) Standby Current (*fS=T1) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT RC OSC) 3/4 3/4 3V 5V 3V 5V 5V 3V No load, ADC off 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V VOL=0.1VDD No load, system HALT LCD off at HALT No load, system HALT LCD on at HALT, C type No load, system HALT LCD on at HALT, C type No load, system HALT LCD on at HALT, R type, 1/2 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/3 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/2 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/3 bias, VLCD=VDD (Low bias current option) 3/4 3/4 3/4 3/4 3/4 3/4 Conditions fSYS=4MHz fSYS=8MHz No load, ADC off fSYS=4MHz No load, ADC off fSYS=4MHz No load, ADC off fSYS=8MHz 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 3.0 6 10 3/4 3/4 1 3 1 3 3 0.3 0.6 3/4 3/4 2.5 10 2 6 17 34 13 28 14 26 10 19 3/4 3/4 3/4 3/4 3.2 3.3 12 25 5.5 5.5 2 5 2 5 5 0.6 1 1 2 5 20 5 10 30 60 25 50 25 50 20 40 0.3VDD VDD 0.4VDD VDD 3.6 3.6 3/4 3/4 V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V mA mA Min. Typ. Max. Unit Ta=25C
IDD1
IDD2
IDD3
IDD4
ISTB1
ISTB2
ISTB3
ISTB4
Standby Current (*fS=32.768kHz OSC)
ISTB5
Standby Current (*fS=32.768kHz OSC)
ISTB6
Standby Current (*fS=WDT RC OSC)
ISTB7
Standby Current (*fS=WDT RC OSC) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Voltage Low Voltage Detector Voltage I/O Port Segment Logic Output Sink Current
VIL1 VIH1 VIL2 VIH2 VLVR VLVD IOL
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HT46R64/HT46C64
Test Conditions Symbol Parameter VDD IOH I/O Port Segment Logic Output Source Current Pull-high Resistance of I/O Ports and INT0, INT1 A/D Input Voltage A/D Conversion Integral Nonlinearity Error Additional Power Consumption if A/D Converter is Used 3V 5V 3V 5V 3/4 3/4 3V 5V 3/4 3/4 3/4 3/4 3/4 Conditions VOH=0.9VDD -2 -5 40 10 0 3/4 3/4 3/4 -4 -8 60 30 3/4 0.5 0.5 1.5 3/4 3/4 80 50 VDD 1 1 3 mA mA kW kW V LSB mA mA Min. Typ. Max. Unit
RPH VAD EAD
IADC
Note:
*fS please refer to clock option of WDT (page 13) Ta=25C Test Conditions Min. VDD Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 3/4 3/4 3/4 400 400 3/4 3/4 0 0 45 32 1 3/4 1 1 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 3/4 3/4 76 32 4000 8000 3/4 3/4 4000 8000 180 130 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz Hz Hz kHz kHz ms ms ms tSYS ms ms tAD tAD 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V Typ. Max. Unit
A.C. Characteristics
Symbol Parameter
fSYS1
System Clock System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency (TMR0/TMR1)
fSYS2 fRTCOSC fTIMER
tWDTOSC Watchdog Oscillator Period tRES tSST tINT tAD tADC tADCS Note: External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time tSYS= 1/fSYS
3/4 3/4 3/4 3/4 3/4 3/4
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HT46R64/HT46C64
Functional Description
Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 12 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses.
T1 T2 T3 T4 T1 T2
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
T3
T4
T1
T2
T3
T4
PC
PC+1
PC+2
. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *11 0 0 0 0 0 0 0 0 *11 #11 S11 *10 0 0 0 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 1 @4 #4 S4 *3 0 0 1 1 0 0 1 1 @3 #3 S3 *2 0 1 0 1 0 1 0 1 @2 #2 S2 *1 0 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 0 @0 #0 S0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Time Base Interrupt RTC Interrupt A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine
PC+2
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
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The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits which are addressed by the PC and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H * Location 008H
Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.
* Location 00CH
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.
* Location 018H
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
000H 004H 008H 00C H 010H 014H 018H 01C H n00H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t R T C In te rru p t A /D C o n v e rte r In te rru p t L o o k - u p ta b le ( 2 5 6 w o r d s ) P ro g ra m M e m o ry
Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H.
* Location 01CH
Location 01CH is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion and the stack is not full, the program begins execution at location 01CH.
* Table location
n..H ...H L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to .
Program Memory
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. Table Location
Instruction(s) TABRDC [m] TABRDL [m]
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits
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HT46R64/HT46C64
These areas may function as a normal ROM depending upon the users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent sixteen return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 2248 bits, and is divided into two functional groups, namely; special function registers 328 bit and general purpose data memory, 1928 bit most of which are readable/writable, although some are read only. The special function register are overlapped in any banks. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0; 0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1 control register (TMR1C; 11H), Interrupt control register 1 (INTC1;1EH), PWM data register (PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH), the A/D result lower-order byte register (ADRL;24H), the A/D result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PDC;19H). The remaining space before the 40H is reRev. 1.00 9
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0.H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1.H 20H 21H 22H 23H 24H 25H 26H 27H 28H ADRL ADRH ADCR ACSR PD PDC PW M0 PW M1 PW M2 PW M3 IN T C 1 TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0
3.H 40H
..H
G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s )
:U nused R e a d a s "0 0 "
RAM Mapping served for future expanded usage and reading these locations will get 00H. The space before 40H is overlapping in each bank. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR
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HT46R64/HT46C64
[m].i. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). The space before 40H is overlapping in each bank. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Interrupts The device provides two external interrupts, two internal timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt and the A/D converter interrupt (NMI). The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags.
Labels C
Bits 0
Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status Register
AC Z OV PDF TO 3/4
1 2 3 4 5 6~7
Rev. 1.00
10
November 17, 2003
HT46R64/HT46C64
Once an interrupt subroutine is serviced, other interrupts except NMI are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request (including NMI) will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the PC onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a an edge transition of INT0 or INT1 (ROM code option: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further maskable interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further maskable interrupts. The non-maskable A/D converter interrupt (NMI) is controlled by EADI (bit 7 of the INT0), when the EADI=1, the A/D converter interrupt will be enabled. If the EADI=0, the A/D converter interrupt will be disable. The NMI cannot be masked by disabling the EMI. After the interrupt is enabled, and the stack is not full, a subroutine call to location 1CH occurs. Function Control the master (global) interrupt (1=enabled; 0=disabled) Control the external interrupt 0 (1=enabled; 0=disabled) Control the external interrupt 1 (1=enabled; 0=disabled) Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Control the A/D converter interrupt (NMI; 1=enable; 0=disable) Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Control the time base interrupt (1=enabled; 0:disabled) Control the real time clock interrupt (1=enabled; 0:disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read as 0 INTC Register
Register
Bit No. 0 1 2
Label EMI EEI0 EEI1 ET01 EIF0 EIF1 T0F EADI ET1I ETBI ERTI 3/4 T1F TBF RTF 3/4
INTC0 (0BH)
3 4 5 6 7 0 1 2
INTC1 (1EH)
3 4 5 6 7
Rev. 1.00
11
November 17, 2003
HT46R64/HT46C64
During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. Except for A/D converter interrupt (NMI). These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time base interrupt Real time clock interrupt A/D converter interrupt (This is a Non-Maskable Interrupt: NMI) Priority 2 3 4 5 6 7 1 Vector 04H 08H 0CH 10H 14H 18H 1CH EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Oscillator Configuration The device provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signal in order to conserve power. The 32768Hz crystal oscillator still runs at HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the HALT mode. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 30kW to 750kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.
V OSC3 OSC1
470p.
DD
The Timer/Event Counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), enable master interrupt bit (EMI), and enable control the A/D converter interrupt (EADI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter 1 interrupt request flag (T1F), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM.
OSC1
OSC4 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r
OSC2 C r y s ta l O s c illa to r
fS
YS
/4
OSC2 RC O s c illa to r
System Oscillator Note: *32768Hz crystal enable condition: For WDT clock source or for system clock source.
Rev. 1.00
12
November 17, 2003
HT46R64/HT46C64
On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to oscillate quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 65ms@5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. Once an internal WDT oscillator (RC oscillator with period 65ms@5V normally) is selected, it is divided by 212~215 (by option to get the WDT time-out period). The minimum period of WDT time-out period is about 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the WDT option, longer time-out periods can be realized. If the WDT time-out is selected 215, the maximum time-out period is divided by 215~216about 2.1s~4.3s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the halt state the WDT may stop counting and lose its protecting purpose. In this situation the logic
S y s te m C lo c k /4 O p tio n fS D iv id e r fS /2
8
can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer The HT46R64/HT46C64 provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranging from fS/22 to fS/29) for the buzzer output by options. It is recommended to select a nearly 4kHz signal for the LCD driver circuits to have proper display. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from 212/fS to 215/fS selected by options. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs.
RTC O SC 32768H z W DT 12kH z OSC
W DT P r e s c a le r O p tio n W D T C le a r CK R T CK R T
T im e 2 15/fS ~ 2 14/fS ~ 2 13/fS ~ 2 12/fS ~
ou 21 21 21 21
tR eset 6/f S 5 /fS 4 /fS 3/f S
Watchdog Timer Rev. 1.00 13 November 17, 2003
HT46R64/HT46C64
fs D iv id e r P r e s c a le r
O p tio n
O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9)
T im e B a s e In te r r u p t 2 12/fS ~ 2 15/fS
Time Base Real Time Clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 2 8* 2 9* 210* 211* 212 2
13
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * LCD driver is still running (if the WDT OSC or RTC
OSC is selected). The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the HALT status, the system cannot be awakened using that interrupt.
214 215
Note: * not recommended to be used Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time clock oscillator).
fS
D iv id e r RT2 RT1 RT0
P r e s c a le r
8 to 1 M ux.
2 8/fS ~ 2 15/fS R T C In te rru p t
Real Time Clock
Rev. 1.00
14
November 17, 2003
HT46R64/HT46C64
If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
100kW RES 10kW 0 .1 m . *
The functional unit chip reset status is shown below. PC Interrupt Prescaler, Divider WDT, RTC, Time Base Timer/event Counter Input/output Ports SP
V
000H Disabled Cleared Cleared. After master reset, WDT starts counting Off Input mode Points to the top of the stack
DD
0 .0 1 m . *
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the PC and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition once the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up. Awaking from the HALT state or system power-up, the SST delay is added. An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the SST delay.
Reset Timing Chart
HALT W DT W DT T im e - o u t R eset E x te rn a l
W a rm
R eset
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
C o ld R eset
Reset Configuration
Rev. 1.00
15
November 17, 2003
HT46R64/HT46C64
The register states are summarized below: Register TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 BP ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA PAC PB PBC PD PDC PWM0 PWM1 PWM2 PWM3 ADRL ADRH ADCR ACSR Note: Reset (Power On) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx 0000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx-- ---xxxx xxxx 0100 0000 1--- --00 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu -xxx xxxx --1u uuuu 0000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx-- ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu -xxx xxxx --uu uuuu 0000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx-- ---xxxx xxxx 0100 0000 1--- --00 RES Reset (HALT) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu -xxx xxxx --01 uuuu 0000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx-- ---xxxx xxxx 0100 0000 ---- --00 WDT Time-out (HALT)* uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu u--0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu uuuu uuuu -uuu -uuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- ---uuuu uuuu uuuu uuuu u--- --uu
Rev. 1.00
16
November 17, 2003
HT46R64/HT46C64
Timer/Event Counter Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains a 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4 or 32768Hz selected by option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are two registers related to the Timer/Event Counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 puts the starting value in the Timer/Event Counter 0 register and reading TMR0 takes the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H) and TMR1C (11H). Writing TMR1L will only put the written data to an
PW M (6 + 2 ) o r (7 + 1 ) C o m p a re fS
YS
internal lower-order byte buffer (8-bit) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L registers, respectively. The Timer/Event Counter 1 preload register is changed everytime there is a writing operation to TRM1H. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the tMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and an active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source.
T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it
8 - s ta g e P r e s c a le r 8 -1 M U X PSC2~PSC0 TM R0 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 0 ) T P A 3 D a ta C T R L O v e r flo w to In te rru p t Q P.D0 f IN
T
D a ta B u s TM 1 TM 0 1 6 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 0
fS Y S /4 32768H z TS M U X TM R1 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 1 6 - b it T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L ) T P A 3 D a ta C T R L O v e r flo w to In te rru p t Q P.D1 f IN
T
D a ta B u s TM 1 TM 0 1 6 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
Timer/Event Counter 1
Rev. 1.00
17
November 17, 2003
HT46R64/HT46C64
In the event count or timer mode, the timer/event counter 0(1) starts counting at the current contents in the timer/event counter 0(1)and ends at FFH(FFFFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, the TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider)
Label (TMR0C)
Bits To define the prescaler stages. PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128
Function
PSC0~ PSC2
0~2
TE TON 3/4 TM0 TM1
3 4 5
Defines the TMR active edge of timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode (TM1, TM0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR0C Register
6 7
Label (TMR1C) 3/4 TE TON TS
Bits 0~2 3 4 5 Unused bit, read as 0
Function
Defines the TMR1 active edge of the timer/event counter (0= active on low to high; 1= active on high to low) Enable/disable timer counting (0= disabled; 1= enabled) Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz) Defines the operating mode (TM0, TM1) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C Register
TM0 TM1
6 7
Rev. 1.00
18
November 17, 2003
HT46R64/HT46C64
output at PA3 by options. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options . No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing SET [PA].3 instruction to enable PFD output and executing CLR [PA].3 instruction to disable PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event counter scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter 0. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. Input/Output Ports There are 24 bidirectional input/output lines in the microcontroller, labeled as PA, PB and PD, which are mapped to the data memory of [12H], [14H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by timer/event counter overflow signal. The input mode always retain its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data register only. Writing 1 to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. The I/O functions of PA3 are shown below. I/O I/P Mode (Normal) PA3 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on)
The PFD frequency is the timer/event counter overflow frequency divided by 2.
The PA0, PA1, PA3, PD4, PD5, PD6 and PD7 are pin-shared with BZ, BZ, PFD, INT0, INT1, TMR0 and TMR1 pins respectively. The PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in output mode of PA0/PA1 will be the buzzer signal generated by multi-function timer. The input mode always remain in its original function. Once the BZ/BZ option is selected, the buzzer output signal are controlled by the PA0, PA1 data register only.
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HT46R64/HT46C64
V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK Q S Q PU
DD
D a ta B it Q D CK S Q M U X P.DEN (P A 3 ) U X O P0~O P7
W r ite D a ta R e g is te r
PA PA PA PA PA PB PD PD PD PD PD PD PD PD
2 3 /P 4~P 0 /A 0 /P 1 /P 2 /P 3 /P 4 /IN 5 /IN 6 /T 7 /T
0 /B Z 1 /B Z .D A7 N 0 ~ P B 7 /A N 7 WM0 WM1 WM2 WM3 T0 T1 MR0 MR1
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2 /P D 3 B Z /B Z /P . D /P W M 0 /P W M 1 /P W M 2 /P W M 3 M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN IN TM TM T0 T1 R0 R1 fo fo fo fo rP rP rP rP D4 D5 D6 D7 on on on on ly ly ly ly
Input/Output Ports The I/O function of PA0/PA1 are shown below. PA0 I/O PA1 I/O PA0 Mode PA1 Mode PA0 Data PA1 Data PA0 Pad Status PA1 Pad Status Note: I I I O OOOOOOOO I I I OOOOO It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. The definitions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad Timer Preload Register State Value OFF OFF ON ON Note: X X N N 0 1 0 1 0 U 0 PFD PFD Frequency X X X fTMR/[2(M-N)]
XXCBBCBBBB XCXXXCCCBB XXD0 I I I D D0 I I 1 D0 0 B D0 0 1 B 0 0 1 B B X D X X X D1 D D X X I D1 D D 0
I input; O output D, D0, D1 Data B buzzer option, BZ or BZ X dont care C CMOS output
The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0/PD1/PD2/PD3. If the PWM function is enabled, the PWM0/PWM1/PWM2/PWM3 signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/PD2/PD3 is operating in output mode). Writing 1 to PD0~PD3 data register will enable the PWM output function and writing 0 will force the PD0~PD3 to remain at 0. The I/O functions of PD0/PD1/PD2/PD3 are as shown. I/O Mode PD0 PD1 PD2 PD3 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1 PWM2 PWM3
X stands for unused U stands for unknown M is 65536 for PFD0 or PFD1 N is preload value for timer/event counter fTMR is input clock frequency for timer/event counter
PWM The microcontroller provides 4 channels (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0/PD1/PD2/PD3. The PWM channels have their data registers denoted as PWM0 (1AH), PWM1 (1BH), PWM2 (1CH) and PWM3 (1DH). The frequency source of the PWM counter comes from fSYS. The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the PD0/PD1/PD2/PD3 are selected as the PWM outputs and the output function of PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/ PDC.2/PDC.3=0), writing 1 to PD0/PD1/PD2/PD3 20 November 17, 2003
Rev. 1.00
HT46R64/HT46C64
data register will enable the PWM output function and writing 0 will force the PD0/PD1/PD2/PD3 to stay at 0. A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter Modulation cycle i (i=0~3) AC (0~3) iThe modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table.
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
(6+2) PWM Mode
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS
YS YS
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
M o d u la tio n c y c le 1
M o d u la tio n c y c le 0
(7+1) PWM Mode Rev. 1.00 21 November 17, 2003
HT46R64/HT46C64
PWM Modulation Frequency fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode A/D Converter The 8 channels and 10 bits resolution A/D (9 bits accuracy) converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion. Define PB configuration, select the converted analog channel, and give START bit a rising edge and falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs. The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered-on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). PWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256 The bit 7 of the ACSR is used for testing purposes only. It can not be used by the users. The bit1 and bit0 of the ACSR are used to select A/D clock sources. Label Bits (ACSR) Function Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined For test mode used only ACSR Register Label Bits (ADCR) ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 EOCB START 0 1 2 3 4 5 6 7 Function
ADCS0 ADCS1
0 1
3/4 TEST
2~6 Unused bit, read as 0 7
Defines the analog channel select. Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is power off to reduce power consumption Provides response at the end of the A/D conversion. (0= end of A/D conversion) Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= reset A/D converter) ADCR Register
ACS2 ACS1 ACS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Analog Channel A0 A1 A2 A3 A4 A5 A6 A7
Analog Input Channel Selection PCR2 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 1 7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 A7 6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 A6 5 PB5 PB5 PB5 PB5 PB5 PB5 A5 A5 4 PB4 PB4 PB4 PB4 PB4 A4 A4 A4 3 PB3 PB3 PB3 PB3 A3 A3 A3 A3 2 PB2 PB2 PB2 A2 A2 A2 A2 A2 1 PB1 PB1 A1 A1 A1 A1 A1 A1 0 PB0 A0 A0 A0 A0 A0 A0 A0
Port B Configuration Rev. 1.00 22 November 17, 2003
HT46R64/HT46C64
When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Register ADRL ADRH Bit7 D1 D9 Bit6 D0 D8 Bit5 3/4 D7 Bit4 3/4 D6 Bit3 3/4 D5 Bit2 3/4 D4 Bit1 3/4 D3 Bit0 3/4 D2
Note: D0~D9 is A/D conversion result data bit LSB~MSB. The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr INTC0.7 ; disable A/D interrupt in interrupt control register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock Start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 Polling_EOC: sz ADCR.6 jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp start_conversion
; reset A/D ; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result from the high byte ADRH register ; save result to user defined register ; read conversion result from the low byte ADRL register ; save result to user defined register ; start next A/D conversion
Example: using Interrupt method to detect end of conversion set INTC0.0 ; interrupt global enable set INTC0.7 ; enable A/D interrupt in interrupt control register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 : : ; interrupt service routine EOC_service routine: mov a_buffer,a mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr ADCR.7 set ADCR.7 clr ADCR.7 mov a,a_buffer reti
; reset A/D ; start A/D
; save ACC to user defined register ; read conversion result from the high byte ADRH register ; save result to user defined register ; read conversion result from the low byte ADRL register ; save result to user defined register
; reset A/D ; start A/D ; restore ACC from temporary storage
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HT46R64/HT46C64
M in im u m o n e in s tr u c tio n c y c le n e e d e d
START EOCB A /D s a m p lin g tim e 3 2 tA D PC R2~PC R0 000B 100B A /D s a m p lin g tim e 3 2 tA D 100B 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n AC S2~ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 7 6 tA D A /D c o n v e r s io n tim e N o te : A /D c lo c k m u s t b e fS
YS
d o n 't c a r e
E n d o f A /D c o n v e r s io n 7 6 tA D A /D c o n v e r s io n tim e
/2 , fS
YS
/8 o r fS
YS
/3 2
A/D Conversion Timing LCD Display Memory The device provides an area of embedded data memory for LCD display. This area is located from 40H to 60H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as 1, any data written into 40H~60H will effect the LCD display. When the BP is cleared to 0 or 1, any data written into 40H~60H means to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device.
COM 0 1 2 3 3 2 40H 41H 42H 43H 5EH 5.H 60H B it 0 1
LCD Driver Output The output number of the device LCD driver can be 332 or 333 or 324 by option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be R type or C type. If the R bias type is selected, no external capacitor is required. If the C bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage can be 1/2 bias or 1/3 bias by option. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins. Refer to application diagram. Option Condition Low Bias Current High Bias Current (Typ.) (Typ.) 1/3 Bias 1/2 Bias (VLCD/4.5)15mA (VLCD/3)15mA (VLCD/4.5)45mA (VLCD/3)45mA
SEGMENT
0
1
2
3
30
31
32
Display Memory
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HT46R64/HT46C64
D u r in g a R e s e t P u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts * * * VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS is u s e d . CD S CD S VLC D VLC D
N o r m a l O p e r a tio n M o d e COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e lig h te d HALT M ode CO M 0,CO M 1,CO M 2 A ll lc d d r iv e r o u tp u ts
CD CD CD CD S S S
VLC D
VLC D VLC D CD CD CD CD CD CD CD CD
VL S CD VL S CD VL S CD VL S CD VL S CD VL S CD VL S CD VL S CD CD S S
VLC D VLC D
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type) LCD Segments as Logical Output The SEG0~SEG23 also can be optioned as logical output, once an LCD segment is optioned as a logical output, the content of bit0 of the related segment address in LCD RAM will appear on the segment. SEG0~SEG7 is together byte optioned as logical output, SEG8~SEG15 are bit individually optioned as logical outputs. LCD Type R Type 1/3 bias 1/2 bias C Type 1/3 bias Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT state, LVR is disabled both LVR and LVD are disabled.
LCD Bias 1/2 Type bias
VMAX
3 If V DD >V LCD , then If VDD > VLCD, then 2 VMAX connect to VDD, connect to VDD, V else VMAX connect to MAX else VMAX connect to VLCD V1
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HT46R64/HT46C64
VA VB VC VSS VA VB VC COM1 VSS VA VB VC COM2 VSS VA VB COM3 VC VSS VA VB L C D s e g m e n ts O N C O M 2 s id e lig h te d N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D VC VSS
COM0
1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D
LCD Driver Output The RTCC register definitions are listed below. Register Bit No. 0~2 3 RTCC (09H) 4 5 6~7 Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock. WDT, RTC and time base clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. Label RT0~RT2 LVDC QOSC LVDO 3/4 Read/Write R/W R/W R/W R 3/4 Reset 0 0 0 0 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillating 0/1: quickly/slowly start LVD detection output (1/0) 1: low voltage detected Unused bit, read as 0
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HT46R64/HT46C64
Options WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or 215/fS~216/fS. CLR WDT times selection. This option defines the method to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 have been executed, the WDT can be cleared. Time Base time-out period selection. The Time Base time-out period ranges from 212/fS to 215/fS fS means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/22~fS/29. fS means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge (bit option). Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. PA, PB and PD can be independently selected (bit option). I/O pins share with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin SEG40 will be set as a common output. LCD bias power supply selection. There are two types of selections: 1/2 bias or 1/3 bias LCD bias type selection. This option is to determine what kind of bias is selected, R type or C type. LCD driver clock frequency selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS stands for the clock source selection by options. LCD ON/OFF at HALT selection LCD Segments as logical output selection, (byte, bit, bit, bit, bit, bit, bit, bit, bit option) [SEG0~SEG7], SEG8, SEG9, SEG10, SEG11, SEG12, SEG13, SEG14 or SEG15 LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options PFD selection. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output INT0 or INT1 trigger edge selection: disable; high to low; low to high; low to high or high to low LCD bias current selection: low/high driving current (for R type only).
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Application Circuits
V
DD
0 .0 1 m . * 100kW 0 .1 m .
10kW
VDD RES
CO M 0~CO M 2 C O M 3 /S E G 3 2 SEG 0~SEG 31 VLC D VMAX
LCD PANEL
LCD
P o w e r S u p p ly
0 .1 m . * VSS
C1 0 .1 m . C2 V
DD
OSC C ir c u it S e e r ig h t s id e
OSC1 OSC2
V1 0 .1 m . R V2
470p.
OSC
OSC1 fS
YS
R C S y s te m O s c illa to r 30kW /4
OSC2 OSC1 C ry s ta l S y s te m . o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
32768H z 10p.
0 .1 m . OSC3 P A 0 /B P A 1 /B PA A 3 /P . A4~PA B 0 /A N B 7 /A N D 7 0 7 ~ P ~ Z Z 2
C1
C2 R1
OSC2
OSC4 P P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 P D 7 /T M R 1 P P
OSC1
P D 0 /P W M 0 P D 3 /P W M 3
OSC2 OSC
32 Os OS un
7 6 8 H z C ry s ta l S y s te m c illa to r C 1 a n d O S C 2 le ft c o n n e c te d
H T 4 6 R 6 4 /H T 4 6 C 6 4
C ir c u it
The following table shows the C1, C2 and R1 value according different crystal values. Crystal or Resonator 4MHz Crystal 4MHz Resonator (3 pin) 4MHz Resonator (2 pin) 3.58MHz Crystal 3.58MHz Resonator (2 pin) 2MHz Crystal & Resonator (2 pin) 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator Note: C1, C2 0pF 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. VMAX connect to VDD or VLCD or V1 refer to the table. LCD Type LCD bias type VMAX R Type 1/2 bias 1/3 bias 1/2 bias If VDD>VLCD, then VMAX connect to VDD, else VMAX connect to VLCD C Type 1/3 bias If VDD > 3/2VLCD, then VMAX connect to VDD, else VMAX connect to V1
Rev. 1.00
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HT46R64/HT46C64
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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HT46R64/HT46C64
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH 2(1) None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
Rev. 1.00
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HT46R64/HT46C64
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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HT46R64/HT46C64
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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HT46R64/HT46C64
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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HT46R64/HT46C64
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. PC PC+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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HT46R64/HT46C64
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
XOR A,[m] Description Operation Affected flag(s)
Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.00
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November 17, 2003
HT46R64/HT46C64
XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.00
43
November 17, 2003
HT46R64/HT46C64
Package Information
56-pin SSOP (300mil) Outline Dimensions
56 A 1 C C'
29 B 28
G H a .
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 720 89 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 730 99 3/4 10 35 12 8
Rev. 1.00
44
November 17, 2003
HT46R64/HT46C64
100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
. A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.00
45
November 17, 2003
HT46R64/HT46C64
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
46
November 17, 2003

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